Verifying Deeds Simulator as a Savvy Tool for Half Adder and Full Adder Circuit Simulation

Falodun Olugbenga Abiola; Aloba Tosin Oluwagbenga; Ayileka Ojo Samson1

1

Publication Date: 2024/09/28

Abstract: Accurate simulation of digital logic circuits is essential for ensuring their functionality before actual hardware implementation. The performance of the Digital Electronic Educational Design System (DEEDS) simulator was evaluated by applying it to half adder and full adder logic circuits. The goal is to assess the precision and dependability of DEEDS by comparing its simulation outcomes with theoretical expectations for these fundamental arithmetic components. This study employs DEEDS to model and simulate these adder circuits, with a focus on comparing the simulation results to theoretical predictions. The verification process involves a thorough examination of the sum and carry outputs for both half adder and full adder circuits across various input scenarios. The analysis identifies any discrepancies between the simulated and theoretical results and explores potential sources of these discrepancies. The results demonstrate that DEEDS offers a reliable and accurate simulation platform for these essential digital circuits, with simulated results closely matching theoretical expectations. This verification highlights DEEDS' effectiveness as a tool for digital circuit design and analysis.

Keywords: Digital Electronics Education And Design Suiter Simulator (DEEDS), Half Adder, Full Adder, Karnaugh Maps.

DOI: https://doi.org/10.38124/ijisrt/IJISRT24AUG608

PDF: https://ijirst.demo4.arinfotech.co/assets/upload/files/IJISRT24AUG608.pdf

REFERENCES

  1. K. Y. Rozier, “Proceedings of the Sixth NASA Langley Formal Methods Workshop Edited by,” no. May, 2008.
  2. W. Hughes, S. Srinivasan, R. Suvarna, and M. Kulkarni, “Optimizing design verification using machine learning: Doing better than random,” arXiv, 2019.
  3. M. S. Daliri, K. Navi, R. F. Mirzaee, S. S. Daliri, and N. Bagherzadeh, “A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates,” IET Circuits, Devices Syst., vol. 11, no. 1, pp. 46–57, 2017, doi: 10.1049/iet-cds.2016.0041.
  4. L. Muntasiroh and I. Y. Afif, “Research on The Application of Digital Electronics Education and Design Suiter Simulator ( DEEDS ) in Electronic Design,” vol. 1, no. November, pp. 103–115, 2022.
  5. K. Johnson Singh, H. Tarunkumar, and T. Sharan, “High speed and low power basic digital logic gates, half-adder, and Full-adder using modified gate diffusion input technology Low-power Low-voltage Operational Transconductance Amplifier Design View project A comparative study on complementary metal oxide,” vol. 8, no. 1, pp. 34–42, 2018, [Online]. Available: www.stmjournals.com
  6. G. Donzellini and D. Ponta, “From gates to FPGA: Learning digital design with Deeds,” Proc. 3rd Interdiscip. Eng. Des. Educ. Conf. IEDEC 2013, pp. 41–48, 2013, doi: 10.1109/IEDEC.2013.6526758.
  7. A. Srinivasulu, “Half Adder Using Different Design Styles: A Review on Comparative Study Half Adder Using Different Design Styles: A Review on Comparative Study View project 2:1 Multiplexer Using Different Design Styles: Comparative Analysis View project Tripti Dua JECRC ,” vol. 7, no. 3, pp. 26–32, 2020, [Online]. Available: www.stmjournals.com
  8. F. J. Anderson, P. Chow, J. Anderson, and J. Anderson, “Digital Systems,” pp. 1–9, 2016.
  9. A. Grover, “Analysis and comparison: Full adder block in submicron technology,” Proc. Int. Conf. Comput. Intell. Model. Simul., vol. 10, no. 6, pp. 197–201, 2013, doi: 10.1109/CIMSim.2013.39.