Publication Date: 2022/03/08
Abstract: This paper aims to implement a RAM which can address itself to load the data into its memory. Using Xilinx 14.1 ISE for simulation and synthesis the RAM of size 16 x 32 is implemented with consecutive addresses generated automatically by the additional circuit in the design.
Keywords: RAM, BRAM, Single Port BRAM, Dual Port BRAM.
DOI: https://doi.org/10.5281/zenodo.6337837
PDF: https://ijirst.demo4.arinfotech.co/assets/upload/files/IJISRT22FEB323_(1).pdf
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