Publication Date: 2021/04/10
Abstract: Over the years, convolutional neural networks have been used in different applications, due to their ability to perform tasks using a reduced number of parameters compared to other in-depth learning methods. However, the use of power and memory constraints, which are often marginal and portable, often conflict with the requirements of accuracy and latency. For these reasons, commercial commercial accelerators have become popular and their design is built on the tendencies of the overall convolutional network models. However, the layout of the gate-mounted gateway represents an attractive view because it offers the opportunity to use a hardware design designed for a particular model of a convolutional network, with promising results in terms of latency and power consumption. In this article, we propose a complete accelerator for chip-programmable gate array hardware for convolutional neural network partition, designed for a keyword recognition system
Keywords: CNN, Accelerator, FPGA.
DOI: No DOI Available
PDF: https://ijirst.demo4.arinfotech.co/assets/upload/files/IJISRT21MAR422.pdf
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