Design and Implementation of PLL with Dead Zone-Less Low-Power Phase Frequency Detector

Gagana T M; Dr. Kiran Bailey1

1

Publication Date: 2024/07/16

Abstract: This project introduces a Phase-Frequency Detector (PFD) that includes a dedicated circuit for removing the dead zone. This design utilizes Pass Transistor Logic (PTL) and Delay Cells (DCs) to effectively address this issue. Additionally, a Low-Pass Filter is integrated into the system and connected with charge pump, employing a technique that replaces resistors with transistors, thereby significantly reducing the overall circuit area. Furthermore, a Phase-Locked Loop (PLL) serves to eliminate the dead zone and significantly reduce the circuit's size. This project aims to advance circuit design methodologies by enhancing performance and minimizing area requirements.

Keywords: Phase Frequency Detector, Low-Pass Filter, Pass Transistor, Delay Cells, Charge Pump, Phase-Locked Loop

DOI: https://doi.org/10.38124/ijisrt/IJISRT24JUN1650

PDF: https://ijirst.demo4.arinfotech.co/assets/upload/files/IJISRT24JUN1650.pdf

REFERENCES

  1. Marichamy Divya1 · Kumaravel Sundaram1, ” Dead zone-less low power phase frequency detector, independent of duty cycle variations for charge pump phase locked loop”, Springer Nature 2023)
  2. Kruti P. Thakore, Dr. Kehul Shah, Dr. N. M. Devashrey, “Design And Implementation of Low Power Phase Frequency Detector For Phase Lock Loop”, IEEE, Proceedings of the Third International Conference on Computing Methodologies and Communication (ICCMC 2019)
  3. Premananda B. S. 1 , Dhanush T. N. 2 , Vaishnavi S. Parashar3 , D. Aneesh Bharadwaj4, “Design and Implementation of High Frequency and Low-Power Phase-locked Loop”, U.Porto Journal of Engineering, 7:4 (2021) 70-86 ISSN 2183-6493 DOI: 10.24840/2183-6493_007.004_0006
  4. Shruti Suman1 , K. G. Sharma2 , P. K. Ghosh3, “Design of PLL Using Improved Performance Ring VCO”, IEEE, International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) – 2016
  5. Zhang Yapeng12 , Ye Tianxiang12 , Qu Zhijuan12, “Design and implementation of a CMOS charge pump phase-locked loop”, 2018 IEEE 4th Information Technology and Mechatronics Engineering Conference (ITOEC 2018)
  6. Sanjana Hokrani, Dr. T. C. Thanuja, Mr. K V Kumaraswamy, “Design and implementation of Phase Locked Loop on 180nm Technology node”, 2018 4th International Conference for Convergence in Technology (I2CT) SDMIT Ujire, Mangalore, India. Oct 27-28, 2018
  7. Alireza Abolhasani, Morteza Mousazadeh *, Abdollah Khoei , “A high-speed, power efficient, dead-zone-less phase frequency detector with differential structure”, Microelectronics Journal 97 (2020) 104719
  8. Anshul Agrawal, Rajesh Khatr, “Design of Low Power, High Gain PLL using CS-VCO on 180nm Technology”, International Journal of Computer Applications (0975 – 8887) Volume 122 – No.18, July 2015